1. Field Of The Invention
The present invention relates to a routing network in a field programmable gate array (FPGA) architecture. More particularly, the present invention relates to a long line routing network employing unidirectional buffers for driving signals onto sets of parallel long routing lines.
2. The Background Art
Programmable logic devices (PLDs) are integrated circuit devices which contain gates or other general-purpose cells whose interconnections can be configured by programming to implement nearly any desired combinatorial or sequential function. Field programmable gate arrays (FPGAs) are well known in the PLD art. FPGAs generally include an array of general-purpose logic circuits, typically referred to as logic blocks, which can be programmed by programmable elements to implement virtually any logic function. The programmed logic elements in the gate array are connected together by routing resources to form a desired integrated circuit. The routing resources are connected to each other and to the logic elements in the gate array by programmable elements.
It is well known in the art that both volatile and non-volatile programmable elements have been used to provide interconnection in FPGA devices. Volatile programmable elements are often a pass transistor controlled by a static random access memory (SRAM) cell. Nonvolatile programmable elements include antifuses and floating gate transistors. Programmable antifuse based architectures and reprogrammable SRAM and floating gate memory cell based architectures as well known in the FPGA art.
In an SRAM based reprogrammable FPGA, the programmable elements are typically passgates controlled by information stored in an SRAM configuration memory. In an antifuse based FPGA, the antifuses are programmable elements that are formed by two conductors with a dielectric material sandwiched in between which represent an open state until programmed. The antifuses are disposed to provide the interconnections among the routing resources and to program the programmable logic elements. In a floating gate transistor based FPGA, the floating gates are typically similar to those used in flash memories the operation of which is well known to those of ordinary skill in the art, but adapted for use in programmable arrays.
A variety of schemes well known to those of ordinary skill in the art for the implementation of the routing network in an FPGA have been proposed in the art. These routing schemes have attempted to address a number of different issues including: reducing the effect of resistance in the routing lines on signal transmission in the circuit; reducing the effect of capacitance between the routing lines on signal transmission in the circuit; increasing the reliability of place and route circuit implementations; and determining the number and lengths of routing lines needed to efficiently utilize the number and granularity of available logic blocks. Granularity is understood by one of ordinary skill in the art to describe the number of inputs into a logic cell, and thereby the complexity of the logic expressions that may be implemented by the logic cell.
In Freeman et al., U.S. Pat. No. 5,594,363, a non-volatile reprogrammable based FPGA is disclosed which discusses the lengths and interconnection of various routing resources, depicted as local, long and global, and the granularity of the logic blocks. The long routing resources are channels that are bidirectional, and the signals on the channels are driven by buffers as the channels transmit the signals. As pointed out in Freeman, et al., the number of active programmable connections on a long routing line is of concern, because they require a not insignificant amount of die area, and also add to the load and capacitance on the line.
In FIG. 1, a schematic example of a known prior art bidirectional routing connection employed in a horizontal long line routing net 10 is illustrated. In the long line routing net 10, first and second horizontal routing nets 12 and 14 are each shown having a routing line, 16 and 18, respectively, being connected to the bidirectional routing connection and a vertical routing net 20 having a routing line 22, that may be connected to the routing line 18 from the second horizontal routing net 14 by a programmable switch 24. In the bidirectional routing connection, the long lines 16 and 18 may be programmably connected to the input and the output of a buffer 26 by programmable switches 28, 30, 32 and 34. The input of buffer 26 may also be programmably connected to ground by programmable switch 36.
In the operation of the bidirectional routing connection depicted in FIG. 1, signals from first horizontal routing net 12 are transmitted to second horizontal routing net 14 when programmable switches 28 and 32 are programmed to conduct, and signals from second horizontal routing net 14 are transmitted to first horizontal routing net 12 when programmable switches 30 and 34 are programmed to conduct. Signals may be transmitted between the vertical routing net 20 and the second horizontal routing net 14 when programmable switch 24 is programmed to conduct. In the event the buffer 26 is not to be used, programmable switch 24 is programmed to conduct. In the event the buffer 26 is not to be used, programmable switch 36 may be employed to pull the input of the buffer 26 to ground. Although not depicted in FIG. 1, a similar bidirectional routing connection is also known to be employed in the vertical direction for vertical long line resources. Active routing repeaters are typically used in longer routing resources, where the distance from on bidirectional routing connection to the next bidirectional routing connection is typically 4 or 8 tiles or even longer.
The bidirectionality of the routing connection is provided by the programmable switches 30 and 32 at the output of the buffer 26 as well as the programmable switches 28 and 34 at the input of the buffer 26. These programmable switches add both serial resistance and switch capacitance to the routing nets. When a very long net is being implemented there can be significant performance degradation resulting from the resistance of the switches 30 and 32 at the output of the buffer 26 due to the increased capacitance imposed by a very long net. Even though the programmable switches 30 and 32 may be implemented as several parallel switches to reduce the serial resistance, the parallel switches add more capacitance and require more die area. Accordingly, it would be advantageous to implement very long line routing nets with buffering as desired while reducing the resistance and capacitance associated with providing connectability between the long line routing nets.